The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Nov. 02, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Riki Suzuki, Yokohama, JP;

Toshikatsu Hida, Yokohama, JP;

Osamu Torii, Setagaya, JP;

Hiroshi Yao, Yokohama, JP;

Kiyotaka Iwasaki, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/35 (2006.01); G06F 11/10 (2006.01); H03M 13/29 (2006.01); G06F 3/06 (2006.01); G11C 29/52 (2006.01); G11C 7/10 (2006.01); G11B 20/18 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
H03M 13/35 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/1008 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/1076 (2013.01); G11C 29/52 (2013.01); H03M 13/29 (2013.01); H03M 13/2906 (2013.01); H03M 13/2957 (2013.01); G11B 20/1833 (2013.01); G11C 7/1006 (2013.01); G11C 2029/0411 (2013.01);
Abstract

According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.


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