Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods

Abstract

Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLKand CLK), where the pulse rate of CLKis slower than that of the CLKand greater than that of CLK. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLKbased on CLKand N-phases of the CLKand a second multi-phase pulse generator can generate N-phases of CLKbased on CLKand N-phases of CLK. Furthermore, additional registers can optionally use the N-phases of CLKto further generate N sets of M-phases of the CLK. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.