The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2019
Filed:
May. 20, 2019
Ningbo University, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Gang Li, Zhejiang, CN;
Huihong Zhang, Zhejiang, CN;
Yuejun Zhang, Zhejiang, CN;
Ningbo University, Zhejiang, CN;
Abstract
Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.