The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Mar. 22, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

See Taur Lee, Allen, TX (US);

Abdellatif Bellaouar, Richardson, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03K 17/687 (2006.01); H03D 7/14 (2006.01); H03K 19/21 (2006.01); H01L 27/12 (2006.01); G01S 7/03 (2006.01); H01L 23/66 (2006.01); H01L 21/84 (2006.01); G01S 13/93 (2006.01); G01S 7/35 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); H03D 7/1466 (2013.01); H03K 17/687 (2013.01); G01S 7/03 (2013.01); G01S 7/35 (2013.01); G01S 13/93 (2013.01); H01L 21/84 (2013.01); H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H01L 29/7838 (2013.01); H01L 2223/6688 (2013.01); H03K 19/21 (2013.01);
Abstract

We disclose frequency doublers for use in millimeter-wave devices. One such frequency doubler comprises at least one passive mixer comprising at least one of the following: at least one transistor configured to receive a back gate voltage; at least one first input driver circuit; and two second input driver circuits. We also disclose a method comprising determining a target output voltage of a frequency doubler comprising at least one passive mixer comprising at least one transistor configured to receive a back gate voltage; determining an output voltage of the frequency doubler; increasing a back gate voltage of the at least one transistor, in response to determining that the output voltage is below the target output voltage; and decreasing the back gate voltage of the at least one transistor, in response to determining that the output voltage is above the target output voltage.


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