The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Apr. 24, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hector Ivan Oporta, San Jose, CA (US);

Shashank Prakash Mane, San Jose, CA (US);

Thomas O'Brien, Powell, OH (US);

Christian Gregory Sporck, Campbell, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/66 (2006.01); G05F 3/02 (2006.01); G06F 13/40 (2006.01); H03K 19/003 (2006.01); H03K 19/0185 (2006.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01R 24/60 (2011.01); H05K 9/00 (2006.01); H02H 9/04 (2006.01); H01R 107/00 (2006.01);
U.S. Cl.
CPC ...
H01R 13/6666 (2013.01); G05F 3/02 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H01L 27/0248 (2013.01); H01L 27/0629 (2013.01); H01R 24/60 (2013.01); H03K 19/00315 (2013.01); H03K 19/0185 (2013.01); H01R 2107/00 (2013.01); H02H 9/041 (2013.01); H02H 9/046 (2013.01); H05K 9/0067 (2013.01);
Abstract

Over-voltage protection systems and methods are disclosed. In one aspect, a biasing circuit is added to a pre-existing clamp required by the Universal Serial Bus (USB) Type-C specification at a configuration control (CC) pin. The biasing circuit turns the pre-existing clamp into an adjustable clamp that dynamically adjusts to over-voltage conditions. In an exemplary aspect, the biasing circuit may include a biasing field effect transistor (FET) and a pair of switches that selectively couple the pre-existing clamp and the biasing FET to fixed voltages such that the CC pin is maintained at an acceptable voltage. In another exemplary aspect, the biasing circuit may omit the biasing FET and rely on two switches that selectively couple the pre-existing clamp to fixed voltages such that the CC pin is maintained at an acceptable voltage.


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