The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Jul. 30, 2016
Applicants:

Sun Yat-sen University, Guangzhou, CN;

Sun Yat-sen University Carnegie Mellon University Shunde International Joint Research Institute, Guangdong, CN;

Inventors:

Kai Wang, Guangzhou, CN;

Hai Ou, Guangzhou, CN;

Jun Chen, Guangzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 31/0224 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78603 (2013.01); H01L 29/42384 (2013.01); H01L 29/66 (2013.01); H01L 29/66477 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H01L 31/022408 (2013.01);
Abstract

The present invention discloses a thin-film transistor structure with a three-dimensional fin-shape channel and a preparation method thereof. The preparation method includes following steps: (a) depositing and etching a bottom gate electrode on a substrate; (b) depositing a bottom dielectric layer at an upper part of a structure obtained from the step (a), and sequentially depositing a semiconductor film on the bottom dielectric layer; (c) etching the semiconductor film to obtain a fin-type channel; (d) respectively depositing an ohmic contact layer, a source electrode and a drain electrode on the semiconductor film located at both sides of the fin-shape channel, and etching; (e) depositing a top dielectric layer and a top gate electrode at an upper part of a structure obtained from the step (d); and (f) etching the top gate electrode, an completing a preparation of a thin-film transistor with a dual-gate three-dimensional fin-shape channel.


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