The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2019
Filed:
Oct. 05, 2017
Applicant:
Futurewei Technologies, Inc., Plano, TX (US);
Inventor:
Jorge Zabaco, San Diego, CA (US);
Assignee:
Futurewei Technologies, Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/28 (2006.01); H02J 5/00 (2016.01); H02J 50/12 (2016.01); H01F 17/00 (2006.01); H01F 41/04 (2006.01); H01F 38/14 (2006.01); H02J 7/02 (2016.01); H04B 5/00 (2006.01);
U.S. Cl.
CPC ...
H01F 27/2804 (2013.01); H01F 17/0013 (2013.01); H01F 38/14 (2013.01); H01F 41/041 (2013.01); H02J 5/005 (2013.01); H02J 7/025 (2013.01); H02J 50/12 (2016.02); H04B 5/0037 (2013.01); H01F 2017/002 (2013.01); H01F 2027/2809 (2013.01); Y10T 29/4902 (2015.01);
Abstract
An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.