The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Jul. 31, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hiroki Nishida, Kamakura, JP;

Hidetaka Tsuji, Yokohama, JP;

Tomoyuki Kantani, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 29/12 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50004 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/12005 (2013.01); G11C 16/34 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01);
Abstract

According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.


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