The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Mar. 06, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Shinichi Yasuda, Setagaya, JP;

Masato Oda, Yokohama, JP;

Kosuke Tatsumura, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G11C 14/00 (2006.01); G11C 5/06 (2006.01); H03K 19/177 (2006.01); G11C 11/419 (2006.01); G11C 11/417 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0054 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); H03K 19/1735 (2013.01); H03K 19/17728 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); G11C 17/165 (2013.01); H03K 19/1737 (2013.01);
Abstract

A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.


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