The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Mar. 27, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Suk-Soo Pyo, Hwaseong-si, KR;

Hyuntaek Jung, Seoul, KR;

Taejoong Song, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 29/50 (2006.01); G11C 11/16 (2006.01); G11C 5/14 (2006.01); G11C 29/02 (2006.01); G11C 7/14 (2006.01); G11C 8/08 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0028 (2013.01); G11C 5/147 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1697 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0033 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 29/028 (2013.01); G11C 29/50 (2013.01); G11C 7/14 (2013.01); G11C 7/227 (2013.01); G11C 8/08 (2013.01); G11C 2013/0054 (2013.01); G11C 2029/5006 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.


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