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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10431287 B1

PDFFull Text
Date of Patent:
Oct. 01, 2019

Filed:

Sep. 15, 2017

Semiconductor memory device including a memory cell with first and second transistors

Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Chika Tanaka, Fujisawa, JP;

Keiji Ikeda, Kawasaki, JP;

Assignee:

Toshiba Memory Corporation, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Hoai V Ho

Int. Cl.
CPC ...
G11C 11/404 (2006.01); G11C 11/4096 (2006.01); G06N 3/04 (2006.01); H01L 27/12 (2006.01); H01L 27/108 (2006.01); G11C 11/56 (2006.01); G11C 7/10 (2006.01); G11C 11/4091 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G11C 11/404 (2013.01); G06N 3/04 (2013.01); G11C 7/1006 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 11/54 (2013.01); G11C 11/565 (2013.01); H01L 27/10805 (2013.01); H01L 27/1225 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.

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Tanaka, Chika. (2019). Semiconductor memory device including a memory cell with first and second transistors (U.S. Patent No. 10431287). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10431287

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