Integrated circuit, and computing system and computer-implemented method for designing integrated circuit

Abstract

A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.