The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Dec. 16, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Chaithanya Dudha, San Jose, CA (US);

Zhao Ma, San Jose, CA (US);

Krishna Garlapati, Los Gatos, CA (US);

Ashish Sirasao, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01);
Abstract

Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.


Find Patent Forward Citations

Dudha, Chaithanya. (2019). Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain (U.S. Patent No. 10430539). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10430539

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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