The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Apr. 12, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kalyan Kumar Oruganti, Vijayawada, IN;

Kailash Digari, Bangalore, IN;

Sandeep Nellikatte Srivatsa, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/16 (2006.01); G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 3/06 (2006.01); G06F 11/20 (2006.01); G06F 1/3234 (2019.01); G11C 11/00 (2006.01); G11C 14/00 (2006.01); G11C 29/32 (2006.01); G06F 1/3287 (2019.01); G06F 9/46 (2006.01); G11C 5/14 (2006.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 11/1666 (2013.01); G06F 1/263 (2013.01); G06F 1/28 (2013.01); G06F 1/3243 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0683 (2013.01); G06F 9/46 (2013.01); G06F 11/2094 (2013.01); G11C 11/005 (2013.01); G11C 14/00 (2013.01); G11C 29/32 (2013.01); G06F 12/0868 (2013.01); G06F 2201/85 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/205 (2013.01); G11C 5/14 (2013.01); Y02D 10/14 (2018.01);
Abstract

An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.


Find Patent Forward Citations

Loading…