The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Oct. 27, 2017
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Irina Calciu, Palo Alto, CA (US);

Jayneel Gandhi, Palo Alto, CA (US);

Pradeep Fernando, Atlanta, GA (US);

Aasheesh Kolli, Palo Alto, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 11/14 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/466 (2013.01); G06F 11/1471 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 3/067 (2013.01);
Abstract

The disclosure provides an approach for atomically executing computer instructions by a CPU of a computing device comprising non-volatile memory, the CPU configured to implement hardware transactional memory (HTM). The approach generally includes reading an instruction within a section of code designated as an HTM transaction, determining whether the instruction causes a data conflict with another thread, and copying cache lines from memory into a cache of the CPU. The approach further includes marking the copied cache lines as transactional, processing the instruction to create a persistent log within non-volatile memory, and unmarking the copied cache lines from transactional, to non-transactional.


Find Patent Forward Citations

Loading…