The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Jun. 26, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Roman Ogirko, Lviv, UA;

Denis Ellis, County Cork, IE;

Kaveh Hosseini, Cork, IE;

Brendan Lawton, Cork, IE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G06F 3/0416 (2013.01); G06F 2203/04101 (2013.01);
Abstract

A capacitance-sensing circuit may include a plurality of channel inputs associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a baseliner component that is coupled to the plurality of channel inputs. The baseliner component may generate a baseline compensation signal using a capacitive circuit and may provide the baseline compensation signal to each of the plurality of channel inputs of the capacitive sense array.


Find Patent Forward Citations

Ogirko, Roman. (2019). Generating a baseline compensation signal based on a capacitive circuit (U.S. Patent No. 10429998). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10429998

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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