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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10426035 B1

PDFFull Text
Date of Patent:
Sep. 24, 2019

Filed:

Mar. 15, 2018

Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern

Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Nan-Jang Chen, Hsinchu, TW;

Yau-Wai Wong, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

Danny Nguyen

Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 23/495 (2006.01); H05K 1/02 (2006.01); H01L 23/31 (2006.01); H02H 9/04 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/18 (2013.01); H01L 23/3185 (2013.01); H01L 23/49503 (2013.01); H01L 23/49524 (2013.01); H01L 23/49531 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49551 (2013.01); H01L 23/49558 (2013.01); H01L 23/49838 (2013.01); H01L 24/49 (2013.01); H02H 9/046 (2013.01); H05K 1/0216 (2013.01); H05K 1/0245 (2013.01); H01L 24/48 (2013.01); H01L 2223/6611 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2224/49109 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/30107 (2013.01); H01L 2924/30111 (2013.01);
Abstract

A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.

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