The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2019
Filed:
Dec. 22, 2017
Applicant:
Raytheon Company, Waltham, MA (US);
Inventors:
Larisa Angelique Natalya Stephan, Los Angeles, CA (US);
David W. Tang, Rancho Palos Verdes, CA (US);
David O. Lahti, Manhattan Beach, CA (US);
Assignee:
Raytheon Company, Waltham, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/17 (2015.01); H01Q 3/26 (2006.01); H04B 17/19 (2015.01); H04W 72/04 (2009.01); H01Q 1/24 (2006.01); H01Q 3/38 (2006.01);
U.S. Cl.
CPC ...
H04B 17/17 (2015.01); H01Q 1/246 (2013.01); H01Q 3/267 (2013.01); H01Q 3/385 (2013.01); H04B 17/19 (2015.01); H04W 72/0453 (2013.01); H04W 72/046 (2013.01);
Abstract
Methods and apparatus to provide clutter rejecting built-in-test and/or fault isolation of individual array elements in assignment-based AESAs. BIT beam states for array element testing can be stored in AESA memory for rapid assignment sequencing of RF waveform generators and receive processing. Simultaneously transmitted signals for BIT sequences have unique signal characteristics that allow test signal clutter rejection on the receive side processing.