The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Aug. 27, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Burt Lee Price, Apex, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/14 (2006.01); H03M 1/36 (2006.01); H03M 7/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/14 (2013.01); H03M 1/365 (2013.01); H03M 7/165 (2013.01);
Abstract

Multiple-bit parallel successive approximation (SA) Flash analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SA Flash ADC circuit includes a digital-to-analog converter (DAC) circuit that receives reference voltage and trial bit codes, and generates DAC analog signals. The SA Flash ADC circuit includes parallel comparator stages, each including one or more comparator circuits equal to two (2) raised to a number of digital bits of the corresponding parallel comparator stage, quantity minus one (1). Each comparator circuit receives an analog input signal and corresponding DAC analog signal, and generates a digital signal. The digital signal of each comparator circuit is logic high if the analog input signal has a greater voltage than the corresponding DAC analog signal, and logic low if the analog input signal has a smaller voltage. The digital signals corresponding to each parallel comparator stage are used to generate a digital output signal.


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