The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2019
Filed:
Dec. 18, 2017
Applicant:
Gsi Technology, Inc., Sunnyvale, CA (US);
Inventors:
Yu-Chi Cheng, Sunnyvale, CA (US);
Patrick Chuang, Sunnyvale, CA (US);
Jae-Hyeong Kim, Sunnyvale, CA (US);
Assignee:
GSI Technology, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/15 (2006.01); H03L 7/081 (2006.01); H03K 5/135 (2006.01); H03L 7/08 (2006.01); H03L 7/16 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1506 (2013.01); H03K 5/135 (2013.01); H03L 7/08 (2013.01); H03L 7/0812 (2013.01); H03L 7/16 (2013.01); H03K 2005/00052 (2013.01);
Abstract
Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.