The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

May. 07, 2018
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Tomohiro Tanaka, Sagamihara, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01);
Abstract

A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.


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