The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Mar. 29, 2018
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventor:

Jeffery Peter Ortiz, Chandler, AZ (US);

Assignee:

Qorvo US Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/52 (2006.01); H03F 3/213 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 1/52 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/213 (2013.01); H03F 3/4508 (2013.01); H03F 2200/165 (2013.01); H03F 2200/171 (2013.01); H03F 2200/267 (2013.01); H03F 2200/451 (2013.01); H03F 2200/541 (2013.01); H03F 2200/93 (2013.01); H03F 2203/21157 (2013.01); H03F 2203/45186 (2013.01); H03F 2203/45228 (2013.01); H03F 2203/45244 (2013.01);
Abstract

A differential power amplifier having first and second amplifiers with first and second signal output terminals along with bias circuitry in communication with the first and second amplifiers is disclosed. The differential amplifier further includes a first output clamp coupled to the first signal output terminal and a bias control terminal of the bias circuitry, wherein the first output clamp is configured to limit voltage at the first signal output terminal to a first predetermined voltage magnitude and lower bias current to the first amplifier in response to an overvoltage at the first signal output terminal. A second output clamp is coupled to the second signal output terminal and is configured to limit voltage at the second signal output terminal to a second predetermined voltage magnitude.


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