The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Feb. 16, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kenneth Dubowski, San Diego, CA (US);

Luverne Ray Peterson, San Diego, CA (US);

Thomas Bryan, Carlsbad, CA (US);

Stephen Knol, San Diego, CA (US);

Sreeker Dundigal, San Diego, CA (US);

Alvin Loke, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 23/485 (2006.01); H01L 23/50 (2006.01); H01L 25/065 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 23/485 (2013.01); H01L 23/50 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 25/0655 (2013.01); H01L 27/0296 (2013.01); H03K 19/017509 (2013.01); H01L 2224/06134 (2013.01); H01L 2224/08135 (2013.01);
Abstract

A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.


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