The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Oct. 19, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Jun Cai, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/408 (2013.01); H01L 21/02238 (2013.01); H01L 21/2652 (2013.01); H01L 21/26586 (2013.01); H01L 29/063 (2013.01); H01L 29/1045 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01);
Abstract

In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.


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