The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2019
Filed:
Jul. 11, 2018
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Tamotsu Ogata, Tokyo, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/11573 (2017.01); H01L 27/11526 (2017.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 27/118 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/0217 (2013.01); H01L 21/76832 (2013.01); H01L 23/5329 (2013.01); H01L 27/11526 (2013.01); H01L 29/42372 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 2027/11831 (2013.01);
Abstract
In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.