The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2019
Filed:
Mar. 26, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/02 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01);
Abstract
Based on a basic idea to effectively utilize a space created in a third wiring layer (M) by a zero-th wiring layer (M) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.