The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Apr. 03, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Tae Il Kim, Goyang-si, KR;

Hyung-Ock Kim, Seoul, KR;

Woo Young Noh, Yongin-si, KR;

Jung Yun Choi, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G03F 7/20 (2006.01); H01L 21/02 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); G03F 7/70483 (2013.01); G03F 7/70616 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); H01L 21/02035 (2013.01);
Abstract

A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering operation on a plurality of pins in a first cell of the cells, based on physical information regarding the pins in the first cell, wherein the physical information is determined based on the placement of the cells, performing a routing operation on the cells after the pin reordering operation, and manufacturing the integrated circuit, based on a layout produced by the routing operation.


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