The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Sep. 24, 2016
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Paul A. Martinez, Morgan Hill, CA (US);

Curtis C. Mead, Sacramento, CA (US);

Scott D. Morrison, Santa Cruz, CA (US);

Giancarlo F. De La Cruz, San Jose, CA (US);

Lin Chen, Saratoga, CA (US);

Albert Wang, Sunnyvale, CA (US);

Brad W Simeral, San Francisco, CA (US);

Vu Vo, Cupertino, CA (US);

Wyeman Chen, Cupertino, CA (US);

Assignee:

APPLE INC., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/232 (2006.01); H01G 4/012 (2006.01); H01G 4/30 (2006.01); H01G 2/06 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01G 4/232 (2013.01); H01G 2/065 (2013.01); H01G 4/012 (2013.01); H01G 4/30 (2013.01); H05K 3/3442 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10636 (2013.01);
Abstract

Systems and methods described in this disclosure are related to fabrication and utilization of two-terminal electrical components that may have terminations with reduced width. Components, such as the ones described herein may be used to increase the density of components in electrical devices, as they may reduce a separation distance between devices that lead to solder bridging. Methods for fabrication are also described, including the use of ceramic layers that may provide reduction in parasitic capacitance and/or inductances.


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