The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Nov. 18, 2016
Applicant:

Ams Ag, Unterpremstaetten, AT;

Inventors:

Carlo Fiocchi, Belgioioso, IT;

Monica Schipani, Pisa, IT;

Assignee:

ams AG, Unterpremstaetten, AT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/575 (2006.01); G05F 1/46 (2006.01);
U.S. Cl.
CPC ...
G05F 1/575 (2013.01); G05F 1/462 (2013.01); G05F 1/465 (2013.01);
Abstract

A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (IS) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F, F) may optionally be provided to improve the phase response.


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