The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2019
Filed:
Sep. 07, 2017
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Yusaku Izawa, Yokkaichi, JP;
Masaki Mae, Yokkaichi, JP;
Assignee:
Toshiba Memory Corporation, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/00 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 27/11548 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
G03F 7/0002 (2013.01); H01L 21/02304 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/11548 (2013.01); H01L 27/11575 (2013.01);
Abstract
According to an embodiment, a template includes steps in first to Nth (N is an integer of 2 or greater) stairs formed in a staircase pattern in a height direction. The steps include first steps in the first to Kth (K is an integer of 1 or greater and N−1 or less) stairs and second steps in (K+1)th to Mth (M is an integer of K+1 or greater and N or less) stairs. A height of the second steps is greater than a height of the first steps.
Izawa, Yusaku. (2019). Template, imprint device, and manufacturing method of semiconductor device (U.S. Patent No. 10423066). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10423066
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile