The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Sep. 10, 2015
Applicant:

Avago Technologies International Sales Pte. Limited;

Inventors:

Gabriel Bracha, Tel-Aviv, IL;

Dikla Tzafrir, Petach Tikva, IL;

Ariel Shchigelski, Ness-Ziona, IL;

Gil Greenstein, Kfar-Saba, IL;

Golan Schzukin, Herzeliya, IL;

Yahav Yechiel Shifman, Hod-Hasharon, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/861 (2013.01); H04L 12/883 (2013.01); H04L 12/863 (2013.01); H04L 12/935 (2013.01);
U.S. Cl.
CPC ...
H04L 49/9052 (2013.01); H04L 47/622 (2013.01); H04L 49/9084 (2013.01); H04L 49/3036 (2013.01); H04L 49/9015 (2013.01);
Abstract

A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.


Find Patent Forward Citations

Bracha, Gabriel. (2019). Hierarchical packet buffer system (U.S. Patent No. 10419370). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10419370

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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