The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Aug. 10, 2015
Applicant:
Zte Corporation, Shenzhen, Guangdong Province, CN;
Inventor:
Yingchun Shang, Shenzhen, CN;
Assignee:
ZTE CORPORATION, , CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 14/00 (2006.01); H04L 7/00 (2006.01); H04J 3/06 (2006.01); H04L 12/26 (2006.01); H04L 12/43 (2006.01); H04Q 11/00 (2006.01); H04L 12/24 (2006.01); H04L 12/751 (2013.01); H04B 10/275 (2013.01); H04L 12/403 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0075 (2013.01); H04B 10/275 (2013.01); H04J 3/06 (2013.01); H04J 3/0623 (2013.01); H04L 12/403 (2013.01); H04L 12/43 (2013.01); H04L 41/12 (2013.01); H04L 43/0852 (2013.01); H04L 45/02 (2013.01); H04Q 11/0066 (2013.01); H04Q 11/0067 (2013.01); H04Q 2011/0045 (2013.01); H04Q 2011/0079 (2013.01); H04Q 2011/0092 (2013.01);
Abstract
Provided are a method and a device for implementing timeslot synchronization. The method includes: a master node performing timeslot synchronization training of an OBTN according to a timeslot length of the OBTN. By adopting the solution provided by the embodiments of the present disclosure, an FDL does not need to be considered in node design, the node design is simplified, the time precision of synchronization is improved and no loss is caused to optical efficiency.