The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

May. 23, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Jung-hyuk Lee, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/24 (2006.01); H01L 43/08 (2006.01); H01F 10/32 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01F 10/3272 (2013.01); H01F 10/3286 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 43/08 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); H01L 45/126 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.


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