The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Jul. 23, 2018
Applicant:
Epistar Corporation, Hsinchu, TW;
Inventors:
Tsung-Hsien Yang, Hsinchu, TW;
Han-Min Wu, Hsinchu, TW;
Jhih-Sian Wang, Hsinchu, TW;
Yi-Ming Chen, Hsinchu, TW;
Tzu-Ghieh Hsu, Hsinchu, TW;
Assignee:
EPISTAR CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/15 (2006.01); H01L 33/08 (2010.01); H01L 33/38 (2010.01); H01L 29/06 (2006.01); H01L 33/00 (2010.01); H01L 33/22 (2010.01);
U.S. Cl.
CPC ...
H01L 27/15 (2013.01); H01L 27/156 (2013.01); H01L 29/0649 (2013.01); H01L 33/08 (2013.01); H01L 33/385 (2013.01); H01L 33/0079 (2013.01); H01L 33/22 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01);
Abstract
A semiconductor device, comprises a semiconductor stack comprising a first area and a second area, wherein the second area comprises a first side wall, a first isolation path formed between the first area and the second area, a second isolation path formed in the semiconductor stack, an isolation layer formed in the first isolation path and covering the first side wall, an electrical contact layer formed under the semiconductor stack, and an electrode contact layer directly contacting the electrical contact layer.