The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Dec. 27, 2017
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Jan Van Houdt, Bekkevoort, BE;

Pieter Blomme, Heverlee, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 27/11521 (2017.01); H01L 21/768 (2006.01); H01L 29/10 (2006.01); H01L 21/3213 (2006.01); H01L 29/66 (2006.01); H01L 27/11556 (2017.01); H01L 27/11568 (2017.01); H01L 21/311 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 27/1159 (2017.01); H01L 27/11597 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02636 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11568 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 29/1037 (2013.01); H01L 29/66545 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/085 (2013.01); H01L 45/124 (2013.01); H01L 45/1233 (2013.01); H01L 27/1159 (2013.01); H01L 27/11597 (2013.01); H01L 27/249 (2013.01);
Abstract

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.


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