The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Nov. 24, 2016
Applicant:

Nsk Ltd., Tokyo, JP;

Inventor:

Shigeru Shimakawa, Tokyo, JP;

Assignee:

NSK LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/367 (2006.01); B62D 5/04 (2006.01); H01L 23/12 (2006.01); H01L 23/36 (2006.01); H05K 1/02 (2006.01); B60R 16/023 (2006.01); H05K 7/20 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); B60R 16/0231 (2013.01); B62D 5/04 (2013.01); H01L 23/12 (2013.01); H01L 23/36 (2013.01); H05K 1/02 (2013.01); H05K 7/209 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device. In the heat dissipation substrate, a plurality of thermal vias are disposed at least in an electronic component projection region in which a region of a bottom surface portion of the electronic component is projected to a mounting surface in a direction perpendicular to the mounting surface, and a surface density of the thermal vias which occupy the mounting surface per unit area is at least partially different. The plurality of thermal vias are disposed so that the surface density of the thermal vias becomes the greatest in a dense region on an inner side of an edge portion of the electronic component projection region.


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