The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 23, 2018
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Vivek Asthana, Noida, IN;

Nitin Jindal, Noida, IN;

Saikat Kumar Banik, Noida, IN;

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 8/12 (2006.01); G11C 29/56 (2006.01); G11C 29/28 (2006.01); G11C 16/04 (2006.01); G11C 29/12 (2006.01); G11C 29/14 (2006.01);
U.S. Cl.
CPC ...
G11C 29/84 (2013.01); G11C 7/065 (2013.01); G11C 7/1012 (2013.01); G11C 8/06 (2013.01); G11C 8/12 (2013.01); G11C 16/04 (2013.01); G11C 29/12 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/28 (2013.01); G11C 29/56012 (2013.01); G11C 29/848 (2013.01);
Abstract

Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.


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