The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Yoichi Minemura, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 27/11568 (2017.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 29/08 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/3459 (2013.01); H01L 23/528 (2013.01); H01L 27/11568 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.


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