The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yuki Inuzuka, Kawasaki Kanagawa, JP;

Tsuneo Inaba, Kamakura Kanagawa, JP;

Takayuki Miyazaki, Tokyo, JP;

Takeshi Sugimoto, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/003 (2013.01); G11C 13/0023 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/148 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01); H01L 27/2481 (2013.01);
Abstract

A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.


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