The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 08, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Karl R. Erickson, Rochester, MN (US);

Phil C. Paone, Rochester, MN (US);

David P. Paulsen, Inver Grove Heights, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/20 (2006.01); G11C 11/419 (2006.01); G11C 29/50 (2006.01); G11C 7/12 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/12 (2013.01); G11C 11/418 (2013.01); G11C 29/50 (2013.01); G11C 2029/5004 (2013.01);
Abstract

Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.


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