The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

May. 15, 2018
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sridhar Kotha, San Jose, CA (US);

Neeraj Parik, San Jose, CA (US);

Harshavardhan Kaushikkar, San Jose, CA (US);

Srinivasa Rangan Sridharan, San Jose, CA (US);

Xiaoming Wang, Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/0871 (2016.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1642 (2013.01); G06F 9/5016 (2013.01); G06F 12/0871 (2013.01); G06F 2212/608 (2013.01); G06F 2213/36 (2013.01);
Abstract

An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.


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