The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

May. 22, 2017
Applicant:

Arm Ltd, Cambridge, GB;

Inventors:

Andrea Pellegrini, Austin, TX (US);

Kshitij Sudan, Austin, TX (US);

Ali Saidi, Austin, TX (US);

Wendy Arnott Elsasser, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/128 (2016.01); G06F 12/0808 (2016.01); G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/128 (2013.01); G06F 12/0808 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 12/12 (2013.01); G06F 2212/621 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01);
Abstract

A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.


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