The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 24, 2017
Applicants:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Wade K. Smith, Sunnyvale, CA (US);

Kostantinos Danny Christidis, Markham, CA;

Assignees:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

ATI TECHNOLOGIES ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); G06F 12/1081 (2016.01); G06F 12/1009 (2016.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 9/3887 (2013.01); G06F 12/1009 (2013.01); G06F 12/1081 (2013.01); G06F 2212/6026 (2013.01); G06F 2212/654 (2013.01); G06F 2212/681 (2013.01); G06F 2212/684 (2013.01);
Abstract

Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.


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