The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Dec. 21, 2017
Applicants:

Jeremy William Horner, Nottingham, MD (US);

Quentin P. Herr, Ellicott City, MD (US);

Inventors:

Jeremy William Horner, Nottingham, MD (US);

Quentin P. Herr, Ellicott City, MD (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0888 (2016.01); H01L 39/22 (2006.01); G06N 10/00 (2019.01); G11C 7/10 (2006.01); G11C 11/44 (2006.01); G11C 8/14 (2006.01); G06F 15/80 (2006.01); G11C 11/419 (2006.01); G11C 8/08 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 12/0207 (2013.01); G06F 15/8038 (2013.01); G06N 10/00 (2019.01); G11C 7/1012 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01); G11C 11/419 (2013.01); G11C 11/44 (2013.01); H01L 39/223 (2013.01);
Abstract

The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being the same as the write address.


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