The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Feb. 23, 2017
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Priyank Faldu, Edinburgh, GB;

Jeffrey Diamond, Austin, TX (US);

Avadh Patel, Cedar Park, TX (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 12/0875 (2016.01); G06F 12/0891 (2016.01); G06F 12/0897 (2016.01); G06F 12/1027 (2016.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 12/0891 (2013.01); G06F 12/0897 (2013.01); G06F 12/1027 (2013.01); G06F 12/12 (2013.01); G06F 2212/452 (2013.01); G06F 2212/68 (2013.01); Y02D 10/13 (2018.01);
Abstract

A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.


Find Patent Forward Citations

Loading…