The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Nov. 08, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jane H. Bartik, Poughkeepsie, NY (US);

Nicholas C. Matsakis, Poughkeepsie, NY (US);

Chung-Lung K. Shum, Wappingers Falls, NY (US);

Craig R. Walters, Highland, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/0842 (2016.01); G06F 12/084 (2016.01); G06F 12/0811 (2016.01); G06F 12/0808 (2016.01); G06F 12/0817 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0828 (2013.01); G06F 2212/602 (2013.01);
Abstract

A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.


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