The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Oct. 22, 2018
Applicant:

Platina Systems Corp., Santa Clara, CA (US);

Inventors:

Frank Szu-Jen Yang, Cupertino, CA (US);

Jason Luo Pang, Cupertino, CA (US);

Eliot Michael Dresselhaus, San Francisco, CA (US);

Dino Farinacci, San Jose, CA (US);

Andreas Demetrios Bovopoulos, Los Gatos, CA (US);

Mark Tehmin Yin, Cupertino, CA (US);

Assignee:

Platina Systems Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2019.01); G06F 1/18 (2006.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01); H04L 12/46 (2006.01); H04L 12/723 (2013.01); H04L 29/06 (2006.01); G06F 1/20 (2006.01); G06F 1/30 (2006.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/183 (2013.01); G06F 1/20 (2013.01); G06F 1/305 (2013.01); G06F 1/3296 (2013.01); G06F 13/36 (2013.01); G06F 13/4068 (2013.01); H04L 12/4633 (2013.01); H04L 45/507 (2013.01); H04L 69/22 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.


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