The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Jul. 06, 2017
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventors:
Geun Ho Choi, Icheon-si, KR;
Hyeong Soo Jeong, Yongin-si, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 1/12 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/10 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 11/4093 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 11/4096 (2013.01); G11C 2207/107 (2013.01);
Abstract
A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.