The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2019
Filed:
Sep. 25, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Karthik Nagarajan, Santa Clara, CA (US);
Chenling Huang, Fremont, CA (US);
Debesh Bhatta, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/093 (2006.01); H03L 7/089 (2006.01); H03K 5/26 (2006.01); H03K 5/1252 (2006.01); H03L 7/07 (2006.01); H03L 7/087 (2006.01); H03L 7/22 (2006.01); H03L 7/23 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03K 5/1252 (2013.01); H03K 5/26 (2013.01); H03L 7/07 (2013.01); H03L 7/087 (2013.01); H03L 7/0891 (2013.01); H03L 7/22 (2013.01); H03L 7/235 (2013.01); H03K 2005/00013 (2013.01);
Abstract
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.