The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Dec. 05, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Shidong Zhou, Milpitas, CA (US);

Sree RKC Saraswatula, Hyderabad, IN;

Jing Jing Chen, San Jose, CA (US);

Teja Masina, Hyderabad, IN;

Narendra Kumar Pulipati, Hyderabad, IN;

Santosh Yachareni, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17736 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01);
Abstract

An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.


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